Model and Algorithm for Fractional Delay HPF Design

Implementing fractional delay filters in FPGA needs a cost-effective approach. This paper tries to clarify a misconception in fractional delay filter design, especially the phase delay and group delay behavior of low pass and high pass filters. Starting with the ideal filter frequency response, followed by practical filter simulation, two important delay factors are compared side by side. Mathematical models and algorithms are derived to establish the relation between phase delay and group delay of high pass filters. Some application tips are given at the end of the paper.